In most conventional data processing systems, a central processor unit (CPU) thereof is generally arranged to operate with its associated memory source units at a synchronous rate which is related to the speed of operation of the memory unit. The memory functions are controlled by the CPU, and the two units are then synchronously operated by the use of appropriate timing signals communicated therebetween.
In such apparatus, the data processing system functions by transferring data among its internal registers, its memory, and its input-output (I/O) devices. The transferring of data involves movement of data between a source and a destination, either directly or through intervening units, such as an arithmetic logic unit (ALU), which appropriately modify the data which is being transferred. The transferring of data with I/O devices occurs over at least one memory bus. In addition, the apparatus has an appropriate independent memory address bus for transferring memory address data.
When memory units associated with the CPU lack synchronous clocks, it is desirable to operate the CPU asynchronously with the memory units, because each of the memory units may operate at a different speed, independent of the CPU operatory speed.
In prior art data processing systems each CPU thereof operates either synchronously or asynchronously with its associated memory units. In the former case, a single clock source is utilized to assure that correct sequencing of the overall data processing operation occurs. In such systems both the CPU and the associated memory units are timed directly from the same clock source. In the latter case, separately and effectively independently operated timing systems, or clocks, are used in the CPU and in its associated memory units. In such asynchronous systems there is no effective relationship between the independently operating clocks. In order to assure that the desired sequence of operations occurs in the CPU and each associated memory unit, the synchronizing of their operations is usually accomplished through appropriate sensing of operating state changes as certain operating signals pass from one binary level to another, such as an edge sensitive synchronizing operations, for example. Relatively elaborate sensing and synchronizing circuitry is usually required for such purpose, and its implementation is relatively expensive.
With most presently known asynchronously operated data processing systems, at least one CPU, and associated control signals used to coordinate its operation with that of its associated memory units are configured so that once a CPU initiates the operation of an associated memory unit, operation of the CPU is effectively halted until an appropriate control signal is received from the associated memory unit to permit resumption of the CPU operations. In such an arrangement, the overall processing time is increased over that which would be required if the CPU were permitted to proceed with at least certain operations simultaneously with the operation of its associated memory units.
In other known data processing apparatus, asynchronous operation is achieved with CPU and associated memory unit clock signals having predetermined phase relationships with each other. The timing between the separate clock pulses of a CPU and each of its associated memory units is asynchronous in the sense that the CPU can operate with associated memory units having different operating speeds, while at the same time the overall timing of each memory unit is made adaptively synchronous to that of its associated CPU because of the predetermined phase relationship between their respective clock pulses. Although this system allows the operation of various memory units at different speeds with a single CPU, separate clocks with a fixed phase relationship are required. In addition, this arrangement requires a clock distribution cable and interface arrangement between the CPU and its associated memory units, just as is the case with synchronous systems. The elimination of this costly addition to the computer system is highly desirable.